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| תיאור: |
Logic Design engineer for the ASIC team, responsible for:
Logic design flow
Backend activities such as Synthesis, Timing analysis, physical design
Chip integration: power supply design, clock network design, timing design and
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| דרישות: |
Education:
B.Sc in EE Engineering
MSC in EE Engineering – Advantage
Technical:
At least 5 years of experience as an ASIC/VLSI designer, performing Logic Design & Back-End
Strong experience in Verification
ASIC timing closure flow including Prime Time-SI.
Knowledge in C++ programming
Basic Physical design experience
Experience in PCI Express
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| היקף המשרה: |
מלאה |
עיר/ישוב: |
נתניה |
תפקיד: |
איש צוות |
שנות ניסיון: |
5 שנים |
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